By Dr. Alec G. Stanculescu (auth.), Randolph E. Harr, Alec G. Stanculescu (eds.)
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Extra resources for Applications of VHDL to Circuit Design
Circuits, Kluwer Academic Publishers, Norwell, MA, 1989. G. S. L. Perry SwitchLevel VHDL Descriptions, ICCAD89. G. S. , VHDL User's Group VHDL Design Exchange Group meeting, February 89.  The Computer Society of the IEEE's DATC Design Automation Standards Committee, The Sense 01 the VASa, Proceedings of the Second Fall User's Group Meeting, October 1989. , March 1988. [131 R. Lipsett, Carl Schaefer, Cary Ussery VHDL: Hardware Description and Design, Kluwer Academic Publishers, Norwell, MA, 1989.
Flake, P. Moorby, G. Musgrave, An Algebra for Logic Strength Simulation, 20th Design Automation Conference, IEEE 1983. [6J P. Flake, P. Moorby, G. Musgrave, Logic Simulation of Bidirectional TN-state Gates, Proc ICCC80, Port Chester, NY pp 594-600. [7J D. Overhauser, 1. Hajj, Y-F. Hsu Automatic Mixed-Mode Timing Simulation, ICCAD89. B. V. N. Trick, LN. Hajj Switch· Level Timing Simulation of MOS VLS! Circuits, Kluwer Academic Publishers, Norwell, MA, 1989. G. S. L. Perry SwitchLevel VHDL Descriptions, ICCAD89.
NQt1>l; c","pu,. " trht . . "cr crr" til. nq. t .... n '_uzfr h ".. '_O"fr •n" .... ,... Ju. V're ,_ (_cell U_ud. 1l H_udr IFlI, '_bo ",cr. ca . , l . nl, '_conv. lor,,)), MUS'''''Q'1»; I. n), '_conv. IdrnlJ, M"S' . ". up <_ 1010• • rt . 1 to; if 01 .. i f p. n". if ,_. . II( . nq. n, if l_...... 1>ldrn. ncr. ncr. if, ancr. if, ",cr. ncr. pZQca . ncr. te and models the speed of commutation. 1. The architecture represents the execution code of the model. It consists of two concurrent statements: a delayed assignment and a process.